Study on the characteristic of the grounding fault on the cascaded midpoint side of the hybrid cascaded HVDC system

1 Introduction

By examining and interpreting power grid data, artificial intelligence (AI) technology can enhance the intelligent management of power grids, thus reducing energy consumption and environmental pollution (Cai et al., 2022; Tang et al., 2022; Wu et al., 2023). The hybrid-cascaded high-voltage direct current (HVDC) transmission technique can effectively reduce power transmission losses, and a combination of the two can boost further the energy utilization efficiency and intelligence of the power grid (Tang et al., 2021; Dong et al., 2023; Liang et al., 2023). In China, the energy distribution is opposite with respect to the center, with bounteous renewable energy sources in the west and developed economies and high-energy demand in the east, and HVDC has numerous potential applications as an important means of large-scale energy transfer. Using the Yangtze Delta area in eastern China as an example, 12-circuit line-mutated converter-based HVDC (LCC-HVDC) landings are located in this area (Zhang et al., 2007). With the commissioning of multiple new LCC-HVDCs, the power grid strength in the Yangtze Delta area of China will be reduced further, thus leading to an increased risk of commutation failure in LCC-HVDC and a gradual reduction in grid voltage stability, which in turn limits the scale of LCC-HVDC development (Shao and Tang, 2017). Following the rapid development of modular multilevel converter-based HVDC (MMC-HVDC) in recent years, the requirements for the recipient grid strength are low, and they have a certain fault ride-through capability; however, its rated voltage and transmission power are not as good as LCC-HVDC, and MMC-HVDC construction costs are higher compared with LCC-HVDC, thus limiting its application scale (Zhu et al., 2021; Saeedifard and Iravani, 2010; Swedesford et al., 2010). Therefore, hybrid HVDC technology, which considers the scale of the AC network as well as the system characteristics and combines the respective benefits of LCC-HVDC and MMC-HVDC, has become a novel technology used to solve the aforementioned problems and a major research focus in the field of HVDC.

The hybrid cascaded HVDC system forms a hybrid transport unit by the series–parallel connection of the LCC and MMCs. The various series–parallel connections of LCCs and MMCs and the location of the hybrid transport unit constitute different topologies of hybrid cascaded HVDC systems, which can be adapted for different applications (Zhao and Iravani, 1994; Torres-Olguin et al., 2012; Haleem et al., 2018). An HVDC system (with an LCC at the rectifier side) and multiple MMCs in parallel (with the LCC in series topology at the inverter side, which has superior DC fault ride-through capability), has been proposed, while the MMCs at the inverter side can provide a certain voltage support capability (Liu et al., 2018; Meng et al., 2021; Qahraman and Gole, 2005). The topology proposed above was used in the ±800 kV Baihetan–Jiangsu HVDC project in China, and the hybrid cascaded HVDC system based on this topology was also evaluated in this study. Related scholars have studied hybrid cascaded HVDC systems using this topology. A coordinated control strategy based on the dynamic limiter, diodes and LCC-MMC active orders is proposed was suggested to improve the AC side voltage stability (Zhao and Tao, 2021). A supplementary coupling mitigation control strategy was suggested to enhance the stability of a hybrid cascaded HVDC system connected to a weak grid (He et al., 2021). A suppression strategy based on fuzzy clustering and an identification method were proposed to repress the DC overcurrent caused by LCC commutation failure at the inverter side (Guo et al., 2021). When an alternating current (AC) short-line fault occurs in the MMC of the hybrid cascaded HVDC system, the imbalanced power between the AC and DC sides of the MMCs will cause capacitor charging of the submodule, which may lead to the blocking of the MMCs. To address the above problems, (Niu et al., 2020), analyzed the mechanism of the MMC submodule’s overvoltage caused by an AC fault and proposed a fault-ride-through strategy based on the fast response of the DC current on the rectifier side. In addition, (Kang et al., 2022), presented a novel method to control the decrease of the adaptive DC voltage that can fully absorb imbalanced power. In the Baihetan–Jiangsu HVDC project in China, a controllable and adaptive energy absorption device was used to absorb surplus power from the DC side to increase the system transient stability (Liu et al., 2021). In addition, considering the MMC overcurrent in DC fault conditions, (Yang et al., 2019), proposed a recovery control strategy for the power regulation of a fixed-active-power MMC. Related studies that have been conducted for hybrid cascaded HVDC systems focused on the solution of the operational characteristics and fault ride-through problems when AC short-line faults occur.

Most previous studies on internal HVDC system faults were conducted on MMC-HVDC: when a short-circuit fault occurs in its DC line, the submodule capacitor discharge and other circumstances will cause a rapid fault-surge current; thus, a reasonable solution for the fault current is needed to provide a basis for the electric design of submodule components in MMC-HVDC (Wang et al., 2011; Wang et al., 2011). When a fault occurs in the DC line of a hybrid cascaded HVDC system, the inverter-side LCC uses its back-blocking characteristics to isolate the fault current fed from the inverter side to the fault point, thus greatly reducing the impact on the HVDC system (Li et al., 2022; Xu et al., 2022). The Comparison of existing contributions and this paper is shown in Table 1. Related studies that have been conducted for hybrid cascaded HVDC systems focused on the solution of the operational characteristics and fault ride-through problems when AC and DC line faults occur.

TABLE 1. Comparison of existing contributions.

The topology of the hybrid cascaded HVDC system shows that the high- and low-end connection line parts of the cascaded side include an area with a negative outlet for the DC filter, a negative outlet for the bypass switch of the high-voltage valve, and a positive outlet for the parallel bus and bypass switch of the low-voltage valve. This area is unique to hybrid cascaded HVDC system by its topology and does not exist in LCC-HVDC and MMC-HVDC. Although the length of the line in this area is shorter than that of the DC line, there are numerous connection parts and the structure is more complex. The lines in this area are mostly arranged in the valve hall, and a general fault occurs, which is a permanent grounding fault. Therefore, it is necessary to carry out a detailed theoretical analysis of fault in this area. Based on the fault section and mode mentioned above, this study proposes a detailed theoretical analysis of the fault responses of the cascaded-side MMC and LCC, divides the fault current evolution process into two steps before and after blocking, and proposes a mathematical calculation method for the fault current. Using an advanced digital power system simulator (ADPSS) as a base, an electromechanical–electromagnetic transient hybrid simulation with a hybrid cascaded HVDC system model was constructed (Tian et al., 2016), and the precision of the theoretical calculation was confirmed based on simulation experiments. Based on the simulation results, the dynamic characteristics of the receiving-end system in fault conditions were analyzed to provide a theoretical basis for equipment selection and power system planning of the hybrid cascaded HVDC system. The conclusions of this study provide important support for the construction of smart grids.

2 Hybrid cascaded HVDC system topology and steady-state control strategy

2.1 System topology

The hybrid cascaded HVDC system adopts a symmetrical wiring form for the positive and negative poles with symmetrical positive and negative structures and consistent parameters; the monopole topology is shown in Figure 1. In Figure 1, U_dr and U_di are the rectifier- and inverter-side DC voltages, U_diL and U_diM are the high- and low-end DC voltages of the high- and low-end voltages at the inverter side, respectively; and L₀ is the smoothing reactor. The rectifier side is composed of two groups of 12-pulse LCCs in series, and the inverter side is composed of LCC and MMCs in series, where the high-voltage valve comprises one group of 12-pulse LCC and the low-voltage valve three parallel MMCs; these three parallel MMCs all adopt half-bridge structures, and the inverter side LCC and each parallel MMCs are associated with different buses of the equal AC network.

FIGURE 1. Single-pole structure of the hybrid-cascaded high-voltage direct current (HVDC) system.

Meanwhile, to reduce the discharge current induced by a DC line short-circuit defect and to reduce the system’s harmonic current, the HVDC system adopts the symmetrical arrangement principle of the pole and neutral lines and sets L₀ on the rectifier and inverter sides, respectively. Table 2 lists the primary parameters of the HVDC system.

TABLE 2. Main parameters of the hybrid-cascaded high-voltage direct current (HVDC) system.

2.2 System control strategy

The methods for both the positive and negative controls were the same in the hybrid cascaded HVDC system. A voltage-dependent current-order limiter (VDCOL), minimum trigger angle control, and constant DC current control were configured on the LCC at the rectifier side (Mao et al., 2021). Based on constant DC voltage control, the LCC on the inverter side is configured with a VDCOL, and it uses constant extinction angle and constant current control as standby controls. The corresponding control structure and switching principle are illustrated in Figure 2A. In Figure 2A, UdiLref and UdiL are the reference and instruction values of the DC voltage at the inverter side, respectively, Idcref and Idcf are the reference and instruction values of the DC current of the HVDC system, respectively, and γmin and γ are the reference and instruction values of the extinction angle at the inverter side, respectively.

FIGURE 2. Control block diagram. (A) Line-mutated converter (LCC) at the inverter side; (B) modular multilevel converter (MMC) at the inverter side.

The parallel MMCs on the inverter side use a DQ axis-based DC vector control approach, which has two control dimensions: one for active control, similar to controlling the active power or DC voltage, and the other for reactive control, similar to controlling the AC bus voltage or reactive power (Saeedifard and Iravani, 2010; Debnath et al., 2014). To guarantee the system’s voltage stability, one of the three parallel MMCs which cooperates with the MMC at the inverter side is selected to adopt constant DC voltage control mode, the other MMCs adopt the control mode of constant active power, and Figure 2B displays the equivalent control block diagram. After determining the control strategies for the rectifier and inverter sides of the hybrid cascaded HVDC system, the static I–V characteristic curve can be obtained, as illustrated in Figure 3. The characteristics of the rectifier side consist of 1, 2, and 3 segments; among these, segment 1 is the minimum trigger angle control characteristic; usually, the minimum value of trigger angle α is taken as 5°; segment 2 is the constant DC current control characteristic, which is also the normal operational characteristic; and segment 3 is the control characteristic of the VDCOL because the low end of the inverter side is the MMC converter, its DC voltage retention characteristics are better, which limits the reduction of the rectifier side voltage. The characteristics of the inverter side are composed of four, five, six, and seven segments; among these, four segments are constant extinction angle control characteristics, with γ set to 15°; five segments are constant DC voltage control characteristics, which are also normal operating characteristics; and six segments are constant DC current control characteristics. To ensure that the DC current control on the inverter side is inoperative during steady-state operation, its current setting value should be lower than the rectifier-side control setting value. Segment 7 is the control characteristic of the VDCOL. In normal conditions, the HVDC system operates at the black point as shown in Figure 3.

FIGURE 3. Static I–V characteristic of HVDC system.

3 Failure mechanism

The fault area in the fault conditions described above is shown in Figure 1, and is mostly arranged in the valve hall; therefore, the general occurrence tends to be a permanent ground fault.

In this study, we built a hybrid simulation model containing a hybrid cascaded HVDC system, including an actual control protection program of the HVDC system. The fault current was obtained, as illustrated in Figure 4, and was based on the model used to simulate the fault in this area.

FIGURE 4. Fault current of HVDC system.

Among them, the actions that play a major role in the transformation of the fault current evolution process include the following.

• Occurrence of failure

• Approximately 10 ms after the failure occurs, MMCs at the inverter side are blocked

• Approximately 40 ms after the failure occurs, the LCC at the rectifier side is forced to undergo a phase shift

From the topology of the hybrid cascaded HVDC system, it is known that after a permanent ground fault occurs in this area, the fault currents originate from the LCC and each parallel MMCs on the inverter side, and are defined as I_dcL and I_dcM, respectively. When the system operates in the steady state, I_dcL and I_dcM are equal. Owing to the manufacturing level, the insulated-gate bipolar transistor (IGBT) and capacitor, which are important components of the MMC submodule, have high costs and weak overcurrent capabilities. Before the MMC is blocked, the IGBT and capacitor have to withstand overcurrents at specific levels; once the IGBT or capacitor are damaged by the overcurrent problem, it will affect the equipment’s life and may endanger the system’s ability to run securely and consistently (Ni et al., 2020). Meanwhile, although the thyristor used in LCC has enhanced overvoltage and overcurrent capabilities, the contact between the HVDC system and the receiving-end system changes significantly during the transient process after a failure occurs (Aik and Andersson, 2018). A theoretical examination of the fault current and system impact in this fault situation is necessary because the power flow of the receiving-end system after a failure differs significantly from that before the failure.

4 Fault current theory analysis of MMCs side

Each parallel MMCs on the inverter side is in normal operation, and there are 2N submodules in the upper and lower bridge arms among which a total of N submodules are in the bypass state, whereas N more submodules are in the input state. It is essentially a time-varying circuit, but during the transient process after a failure occurs, the DC voltage of the MMCs does not increase suddenly; therefore, it can be assumed that each phase’s input of the submodules will always have the same number, that is, the equivalent capacitance of any phase is constant. MMCs can be considered linear circuits during this time and can be analyzed using the superposition theorem.

4.1 State before MMCs are blocked

During fault response analysis, the fault current is the sum of three parallel MMC fault currents. The MMCs have the same primary parameters on both sides and are connected to different nodes in the same AC network. The voltage amplitude and phase angle of each MMC are approximately the same. To facilitate the calculations, we assumed that the voltage amplitudes and phase angles of the three parallel MMCs were identical. Taking MMC1 as an example to begin the analysis, the time-domain model is shown in Figure 5.

FIGURE 5. Time domain model of MMC1.

The complicated frequency-domain model of MMC1, shown in Figure 5, transforms the time-domain model into an arithmetic circuit model, as shown in Figure 6A, where the impedances of the grounding electrode line and smoothing reactor L0 were unified and combined as Rg + jwLg. The excitation sources are shown in Figure 6A were separated as follows.

• DC side excitation source

• AC side excitation source

FIGURE 6. (A) Complex frequency domain model of MMC1; (B) response circuit of DC excitation source.

The fault current on the MMC₁ side is the outcome of the synergistic work of the two types of excitation sources described above. Therefore, the two types of excitation sources above were decomposed, the response of each group of excitation sources (acting separately) was calculated according to the principle of the superposition theorem, and the total response of the MMC₁ circuit was obtained by summing them.

4.1.1 Response of DC side excitation source

The excitation source for this part of the response circuit consists of three parts: all-submodule capacitors, the excitation source matching the initial value of I_dc in the bridge arm reactor, and the source of excitation for the starting value of the current in the smoothing reactor. The DC-side excitation-source response circuit is shown in Figure 6B.

To solve this part of the excitation source response, the following simplifications were made.

• In this part of the response, there is no excitation source in the three-phase symmetric AC network. Therefore, the role of the AC network can be disregarded when analyzing the DC line’s current

• Each submodule can be considered to have the same capacitance voltage Uc based on the principle of constant-capacitance storage in each submodule. The equivalent capacitance of each phase bridge arm Ceq is expressed as follows,

Additionally, considering that U_diM = N_cU_c, it is obtained that

Based on the simplification principle above, the DC-side excitation source circuit of MMC₁ can be simplified as follows,

As the major part of the circuit is a parallel connection of nine phase units and the lower end of the inverter side is linked in parallel with three groups of MMCs, the circuit of this part may be simplified, as shown in Figure 7B. By solving this simplified circuit, the fault current of the MMCs subject to the response of the excitation source in the complex frequency domain is obtained as follows,

FIGURE 7. Simplified circuit of the DC side excitation source. (A) MMC1; (B) three parallel MMCs.

The fault current I_dcm(t) is obtained by substituting the specific parameters of the HVDC system and the system state quantities into the I_dcM(s) expression and performing the inverse Laplace transform. In addition, because of the symmetry of each phase unit, I_dcm(t) is spread equally throughout the phase units, and the current flowing in each bridge arm is I_dcm(t)/9.

where τ₁ is the time constant of the current decay, ω₁ is the resonant frequency, and θ₁ is the initial phase angle. These parameters are determined by the system parameters.

4.1.2 Response of AC side excitation source

The excitation source for this section of the response circuit consisted of an AC network equivalent power supply, an excitation source allied with the initial value of the inductor current, and an excitation source allied with the initial value of the AC current in the bridge arm reactor. The response circuit is shown in Figure 8A.

FIGURE 8. Circuit of the AC excitation source. (A) Response circuit and (B) simplified circuit.

Because the equivalent power supply of the AC network and the entire circuit configuration are three-phase symmetric, no current enters the DC line from the AC side. The response circuit was simplified according to this principle, as shown in Figure 8B.

Each bridge arm in each phase carries half of the current on the AC side. When phase A of the upper bridge arm of MMC₁ is used for analysis, the expression of the equivalent source of phase A is assumed to be u_sa(t) = E sin (ω₀ t). The upper bridge arm’s response expression is,

Among them

In summary, the total response process of the MMCs before blockage can be obtained. It is evident from the above study that the fault current on the MMCs side is related only to the DC-side excitation source response. The response process is described in (4), (5), (6). From the calculation of ω₁, it is evident that the fault current reaches a peak approximately 17 ms after a failure occurs. However, the MMCs were prompted to block approximately 10 ms after failure; therefore, the fault current before blocking increased monotonically. The fault current calculated by (4) was 11.7 kA at 10 ms after failure occurred and matches the simulation results in Figure 4.

4.2 State after MMCs are blocked

In a hybrid cascaded HVDC system, three parallel MMCs transmit power to the DC side. Using the present direction of Figure 5 as an illustration, there exists a DC bias with a value of 1/9 I_dcM for each phase of the upper bridge arm current i_pj and a DC bias with a value of −1/9 I_dcM for each phase of the lower bridge arm current i_nj. Before the MMC is triggered to block, the fault current at the MMCs and the bridge arm current of each phase mainly originate from the DC-side excitation source response. The rate of change of this current is extremely fast, which makes the I_dcM change from negative to positive within milliseconds, while the reversal process of I_dcM also delays the time for the fault current to reach its peak to a certain extent. After the MMCs were blocked, the flow path and pattern of the fault current changed. It is also an important part of the complete response of the HVDC system after the failure occurs. The following is an example of MMC₁ for fault current change characteristic analysis after blocking.

As shown from the topology, each submodule of MMC₁ uses the half-bridge topology. After the blocking command is issued, each submodule is in a blocking state, and there are two operation modes in this state due to the renewal of the antiparallel diodes D₁ and D₂ in each submodule. In the first operation mode, D₁ is on and current passes through D₁ to charge the capacitor. In the second mode of operation, D₂ is turned on, and the current passes through D₂ to bypass the capacitor.

Because the sum voltage of the capacitors on each bridge arm in MMC₁ is greater than the AC voltage amplitude, each submodule operates as illustrated in Figure 9B. Before the bridge-arm current reaches zero, the antiparallel diodes of the upper and lower bridge arms operate in the conducting state, and the single-phase conductivity of the antiparallel diodes is not considered. Compared with MMC₁ before blocking, the DC-side excitation source response changed into a persistent current circuit in the bridge arm reactor. The remaining two excitation source circuits remained unchanged, and the three excitation source responses were superimposed to produce the bridge arm current. Figure 10.

FIGURE 9. Operation mode of MMCs in the blocking state. (A) Charging and (B) bypassing the capacitor.

FIGURE 10. Bridge arm current of MMC1.

After this part of the current decays to zero for the first time, the antiparallel diode cannot operate. The upper and lower bridge arm currents are switched from a two-way flow to a one-way flow limited by the antiparallel diode; at this time, the three-phase uncontrolled rectifier circuit begins its steady-state operation phase.

In a three-phase uncontrolled rectifier circuit, the conduction instant of the antiparallel diode on each phase bridge arm is the intersection of the phase voltage of that phase with that of the adjacent phase (i.e., the natural phase-change point). In the steady-state operation phase after MMC₁ is blocked, any phase bridge arm midpoint voltage is greater than zero because of the MMC₁ fault ground at the high-tension side, and the phase on the bridge arm’s antiparallel diode meets the conduction conditions; thus, the upper bridge arm conducts. In addition, if the midway voltage of the bridge arm of the phase changes from positive to negative, the antiparallel diode will not immediately arc out owing to the current-continuing bridge arm reactor but will continue to conduct for a while and then turn off.

Define θ_arm as the angle of continuous conduction of each bridge arm. Based on the above analysis, θ_arm > π; additionally, define the sum of the inductance of each phase bridge arm in the uncontrolled rectifier as L_sum. It is known from Figure 11 that L_sum = L_arm + L_s. Owing to the different ratios of R_g to L_arm, the θ_arm values are different (Li et al., 2016); this leads to different operating response characteristics. When R_g/L_sum > 100, π ≤ θ_arm < 4π/3, and the operating response is alternating between three and four bridge arm conduction. When R_g/L_sum ≤ 100, θ_arm ≥ 4π/3, and the operating response is alternating between four and five bridge arms conduction. According to the calculation of the parameters of the HVDC system, R_g/L_sum is much less than 100; therefore, the steady-state operating response characteristics of MMC₁ after blocking are based on alternate switch-on operations of four and five bridge arms, and the angle of continuous conduction of each bridge arm can be found as follows,

FIGURE 11. Response circuit after MMC1 is blocked.

Utilizing the antiparallel diode D₁’s conduction as the starting point, the analytic expression for the current in one power frequency period was analyzed. The steady-state circuit after the MMC is blocked, as shown in the figure, and always conducts and opens according to the conduction sequence D₁-D₂-D₃-D₄-D₅-D₆-D₁. Before D₁ was set, D₃, D₄, D₅ and D₆ were tested. According to the circuit analysis, this period satisfies the following expression,

Meanwhile, according to Kirchhoff’s current law, it is obtained that

Substitution of (11) into (10) yields,

LLet the phase A equivalent source expression be u_sa(t) = E sin (ω₀ t). Then, when ω₀ t = 0, it satisfies i_pa = 0. By substituting this initial condition, the phase-A upper bridge arm current under this conduction condition can be obtained as follows,

Thereafter, the operating response of the bridge arm current is defined by the alternative operation of the four- and five-bridge arm conductions; thus, the above analysis method can be used to solve all conduction conditions to obtain an analytical expression for the current in one power frequency period as follows,

Based on the operating response characteristics of the different stages after MMC₁ is blocked and the conduction of each bridge arm, the fault current of MMC₁ can be determined as follows,

In conclusion, it was possible to determine MMC₁’s steady-state operational response properties. The angle of continuous conduction of each bridge arm was calculated to be equal to 280° by (9), MMC₁ fault current was calculated to be 7.87 kA using (15), and the fault current I_dcM provided by each parallel MMCs was 23.6 kA, which coincides with the simulation results in Figure 5.

5 Fault current theory analysis of LCC side

From the topology of the HVDC system, the LCC fault current I_dcL is equal to I_dc and is expressed as

where U_dr and U_di are the DC voltages within L₀ on the rectifier and inverter sides, and R_line and L_line are the DC line impedances, respectively. The differential term in (16) is zero during the steady-state operation; therefore, I_dc is related only to the difference between U_dr and U_di. The differential term is not zero after a failure occurs, and its solution is obtained as follows,

where τ_L = L_dc/R_dc. Expanding for U_di, we obtain

where N_i is the number of 6-pulse LCC converters in each pole, U_sL is the LCC bus line voltage at the inverter side, k_rL and X_sL are the LCC converter transformer ratio and leakage resistance at the inverter side, respectively, and β is the advanced LCC trigger angle of the inverter side.

After a failure occurs, the system’s triggers a blocking fault-pole strategy. Meanwhile, the pole control system sends a blocking command to each valve control system running the LCC after receiving the pole-blocking command from the station or the opposite station. During this process, the LCC on the rectifier side is forced to shift the phase to accelerate the fault current decay. Therefore, the LCC-side fault response is also discussed in two phases: before and after the forced phase shift of the LCC on the rectifier side.

5.1 State before forced phase shift

When the AC voltage at the inverter side is lowered, a constant extinction angle control is utilized to lower the possibility of commutation failure. Constant current control is employed to keep the I_dc flowing when the rectifier side experiences a defect and to speed up power recovery after a failure has occurred. During steady-state operation, U_diL and U_diM were both 400 kV, U_di was approximately 800 kV, and γ_iL was greater than 15°. The output signal of the constant extinction angle control was negative, and the output signal of the constant DC voltage control was zero; therefore, the constant extinction angle control did not operate.

After the fault occurred, U_di decreased to ∼400 kV. Eq. 17 shows that a significant decrease in U_di after a failure leads to an increase in I_dc. From the commutation principle of the LCC, it is known that there is a relationship between μ_iL, γ_iL, and β_iL,

The increase in I_dc causes μ_iL to increase and γ_iL to decrease, thus resulting in a) the output <0 in the constant DC voltage control side, b) an output signal of the constant extinction angle control side <0, and c) the LCC at the inverter side moving to constant extinction angle control. Simultaneously, when γ_iL < γ_min, the LCC on the inverter side induces a commutation failure. The LCC extinction angle on the inverter side during a fault is shown in Figure 12A.

FIGURE 12. (A) LCC extinction angle at the inverter side; (B) LCC trigger angle at the rectifier side.

Unlike general AC system faults at the inverter side, which cause commutation failure induced by voltage dips at the commutation bus, the same problem of commutation failure is induced at the internal fault conditions of the HVDC system. However, the essence is that the increase of I_dc causes the increase of the μ_iL and the decrease of t γ_iL, thus resulting in γ_iL values < γ_min.

5.2 State after the forced phase shift

After receiving the pole blocking command, the LCC system adopts the forced phase shift strategy to reduce U_dr to a negative value so that the HVDC system’s energy can be promptly transferred back to the AC system. This helps I_dcL decay to zero quickly. During the initial stage, after the forced phase shift of the LCC at the rectifier side, the trigger angle increased to 120° instead of 165° to avoid commutation failure induced by small phase-change angles after entering the inverted state. When I_dc was detected to be lower than 0.05 p. u., after a time delay, the LCC triggered phase-shift locking.

6 Characterization of the AC network at the receiving end

After failure occurs, it is clear from the above analysis that U_dr reduces to a negative value during the blocking process through a forced phase-shift strategy, which helps I_dcL decay to zero quickly, thus ensuring that the LCCs on the rectifier and inverter sides are reliably blocked and have no power interaction with the AC side after blocking. Figure 13.

FIGURE 13. (A) Total power and (B) LCC power responses.

On the inverter side, each parallel MMC uses a constant reactive power regulation method, and the reactive power interaction between the MMCs and the AC network is nearly zero before failure occurs. After the MMCs are blocked, the submodule capacitor no longer provides fault currents to the fault point. However, the AC network can still provide fault currents, and the converter leakage resistance and bridge arm reactance of the MMC consume a significant amount of reactive power.

From the receiving-end grid VQ curve of the reactive power supply and load, the load reactive power suddenly increases significantly, and the load VQ curve shifts upward (Liu et al., 2016). If the reactive power supply capacity is insufficient, the voltage at the new intersection of the VQ curves of the reactive power supply and the load decreases, thus forcing the reactive power supplier to increase the output of Q and the load side to decrease consumption. Thus, the receiving-end grid reaches a new stable balance state at a low-voltage level, and the AC bus voltage of each parallel MMC side is shown in Figure 14B.

FIGURE 14. (A) Reactive power response of MMCs; (B) busbar voltage responses of MMCs.

Therefore, because of the slow opening and shutting times of the AC switch, the MMC approximates a three-phase uncontrolled rectifier, and its converter leakage resistance and bridge arm reactance must consume a large amount of Q. If the reactive power capacity is insufficient, the voltage at each node is reduced. The simulation results show that if the responses of the long-term dynamic components and parts are not considered, the AC network does not meet the relevant long-term voltage stability evaluation criteria.

7 Conclusion

This study used a hybrid cascaded HVDC system as the research object and simulated a permanent ground fault in high- and low-end connecting lines on the cascaded side. It then conducted a thorough theoretical analysis of the fault responses of MMCs and LCCs as well as the impact of the AC network. The relevant conclusions are as follows:

The fault current on the MMC₁ side was the result of the combined action of the aforementioned two types of excitation sources. Therefore, the two types of excitation sources were decomposed, the response of each group of excitation sources acting separately was calculated according to the principle of the superposition theorem, and the total response of the MMC₁ circuit was obtained by adding them together.

• Because of the reliable blocking of the MMCs and the reverse process of I_dcm, there was no need to consider the IGBT overcurrent of each submodule before the MMCs were blocked

• The LCC on the inverter side may lead to commutation failure owing to the increase in I_dc in the fault conditions described above

• During the steady-state process, after the MMCs were blocked, the HVDC system consumed a significant amount of reactive power; this resulted in a reduction in the AC voltage at the receiving grid. This does not satisfy the relevant long-term voltage stability evaluation criteria.

From the calculation and simulation results, the theoretical analysis presented above yielded results that were consistent with the actual response, thus providing a theoretical basis and calculation method for the design, testing, and performance evaluation of HVDC systems. In addition, the HVDC system is a significant part of smart grids in the broad range of applications of AI and there is a close connection between the two. The theoretical analysis presented above can also realize intelligent management and control of power systems, improve the energy utilization efficiency and stability of the power grid, and provide strong support for energy transformation. In the future, further research will be conducted in terms of reducing the overcurrent peak of the bridge arm after the failure occurs.

Data availability statement

The original contributions presented in the study are included in the article/supplementary material, further inquiries can be directed to the corresponding author.

Author contributions

YR, HS, SW, BZ, and SX was responsible for contributing conception and design of the study and writing sections of the manuscript. YR wrote the first draft of the manuscript. ML and PL was responsible for model building, simulation. All authors participated in the reading and approved the submitted version.

Funding

This research was funded by the National Natural Science Foundation of China under integration project (U216660003).

Conflict of interest

YB, SW, BZ, SX, ML, and PL were employed by China Electric Power Research Institute Co. Ltd.

The remaining author declares that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

References